1. Field of the Invention
The invention relates to a thermally enhanced three-dimensional package, and more particularly, to a three dimensional package utilizing a heat sink on a first chip package to position another chip package.
2. Description of the Prior Art
In conventional semiconductor packages, three dimensional packages fabricated by stacking a plurality of chip packages over one another are commonly utilized to achieve multi-functional purpose. However, as the chip packages generate large amounts of heat during operation, a heat sink is often installed to maintain the three dimensional package at a normal working temperature. Additionally, a boat is utilized to position the chip packages while stacking the chip packages over one another. This will unavoidably increase the overall cost. Moreover, a slight miscalculation in the size of the boat or the edge of the substrate of the chip packages will result in a cold joint issue and unsuccessful bonding of the chip package, and as the chip packages undergo numerous reflow processes, a warpage phenomenon will often result.
Please refer to FIG. 1. FIG. 1 is a perspective diagram showing a cross-section of a conventional three-dimensional package. As shown in FIG. 1, the three-dimensional package 100 includes a first chip package 110, a second chip package 120, a plurality of solder balls 130, and a plurality of external conductive devices 140. Preferably, the first chip package 110 includes a first substrate 111 and a first flip chip 112, in which the first substrate 111 includes a top surface 113 and a bottom surface 114. The flip chip 112 is connected to the bottom surface 114 of the first substrate 111 by utilizing a plurality of bumps 115, in which the bumps 115 are sealed by an underfill layer 116. Similarly, the second chip package 120 includes a second substrate 121 and a second flip chip 122, in which the second substrate 121 includes a top surface 123 and a bottom surface 124. The second flip chip 122 is connected to the top surface 123 of the second substrate 121 by utilizing a plurality of bumps 125, in which the bumps 125 are sealed by an underfill layer 126. Additionally, the solder balls 130 are formed between the top surface 113 of the first substrate 111 and the bottom surface 124 of the second substrate 121 to electrically connect the first chip package 110 and the second chip package 120, and the external conductive devices 140 are disposed on the bottom surface 114 of the first substrate 111 for connecting to other electronic devices (not shown).
Essentially, the first chip package 110 and the second chip package 120 of the three-dimensional package 100 often generate significant amounts of heat during operation thereto reducing the performance of the device as a result of overheating. Additionally, phenomenon such as warpage occurs frequently on the first chip package 110 and the second chip package 120 and influences the structural sturdiness and electrical transmission of the three-dimensional package 100. Furthermore, when the first chip package 110 and the second chip package 120 are stacked over each other, a boat is commonly utilized to position the first chip package 110 and the second chip package 120, thereby increasing cost and reducing over yield.